Preliminary Specifications: Programmed Data Processor Model Three Part 4

The overflow flip-flop is cleared by the "Start" Switch.

_Skip on Plus In-Out Register_ (5 usec.) spi Address 2000

If the sign digit of the In-Out Register is ZERO the Program Counter is indexed one extra position and the next instruction in the sequence is skipped.

_Skip on ZERO Switch_ (5 usec.) szs Addresses 10, 20, ... 70

If the selected Sense Switch is ZERO, the Program Counter is advanced one extra position and the next instruction in the sequence will be skipped. Address 10 senses the position of Sense Switch 1, Address 20 Switch 2, etc. Address 70 senses all the switches. If 70 is selected all 6 switches must be ZERO to cause the skip to occur.

_Skip on ZERO Program Flag_ (5 usec.) szf Addresses 0 to 7 inclusive

If the selected program flag is a ZERO, the Program Counter is advanced one extra position and the next instruction in the sequence will be skipped. Address 0 is no selection. Address 1 selects program flag one, etc. Address 7 selects all programs flags. All flags must be ZERO to cause the skip.

The instructions in the One Cycle Skip group may be combined to form the inclusive OR of the separate skips. Thus, if address 3000 is selected, the skip would occur if the overflow flip-flop equals ZERO or if the In-Out Register is positive. The combined instruction would still take 5 microseconds.

_Operate Group_ (5 usec.) opr Y Operation Code 76

This instruction group performs miscellaneous operations on various Central Processor Registers. The address portion of the instruction specifies the action to be performed.

_Clear In-Out Register_ (5 usec.) cli Address equal 4000

This instruction clears the In-Out Register.

_Load Acc.u.mulator from Test Word_ (5 usec.) lat Address 2000

This instruction forms the inclusive OR of the C(AC) and the contents of the Test Word. This instruction is usually combined with address 200 (clear Acc.u.mulator), so that C(AC) will equal the contents of the Test Word Switches.

_Complement Acc.u.mulator_ (5 usec.) cma Address 1000

This instruction complements (makes negative) the contents of the Acc.u.mulator.

_Halt_ hlt Address 400

This instruction stops the computer.

_Clear Acc.u.mulator_ (5 usec.) cla Address 200

This instruction clears (sets equal to plus 0) the contents of the Acc.u.mulator.

_Clear Selected Program Flag_ (5 usec.) clf Address 01 to 07 inclusive

The selected program flag will be cleared. Address 00 selects no program flag, 01 clears program flag 1, 02 clears program flag 2, etc. Address 07 clears all program flags.

_Set Selected Program Flag_ (5 usec.) stf Address 11 to 17 inclusive

_In-Out Transfer Group_ (5 usec. without in-out wait) iot x Y Operation Code 72

The variations within this group of instructions perform all the in-out control and information transfer functions. If bit six (normally the Indirect Address bit) is a ONE, the computer will halt and wait for the completion pulse from the device activated. When this device delivers its completion, the computer will resume operation of the instruction sequence.

An incidental fact which may be of importance in certain scientific or real time control applications is that the time origin of operations following an in-out completion pulse is identical with the time of that pulse.

Most in-out operations require a known minimum time before completion.

This time may be utilized for programming. The appropriate In-Out Transfer is given with no in-out wait (bit six a ZERO). The instruction sequence then continues. This sequence must include an iot instruction which performs nothing but the in-out wait. This last instruction must occur before the safe minimum time. A table of minimum times for all in-out devices is delivered with the computer. It lists minimum time before completion pulse and minimum In-Out Register free time.

The details of the In-Out Transfer variations are listed under Input-Output.

The mnemonic codes and addresses for the standard equipment are:

_Read Paper Tape Alphanumeric Mode_ rpa Address 1

_Read Paper Tape Binary Mode_ rpb Address 2

_Typewriter Output_ tyo Address 3

_Typewriter Input_ tyi Address 4

_Punch Paper Tape Alphanumeric Mode_ ppa Address 5

_Punch Paper Tape Binary Mode_ ppb Address 6

MANUAL CONTROLS

The Console of PDP-3 has controls and indicators for the use of the operator. Fig. 4 is a close-up of the control panel of PDP-1, the 18 bit version of PDP-3. All computer flip-flops have indicator lights on the Console. These indicators are primarily for use when the machine has stopped or when the machine is being operated one step at a time. While the machine is running, the brightness of an indicator bears some relations.h.i.+p to the relative duty factor of that particular flip-flop.

Three registers of toggle switches are available on the Console. These are the Test Address (15 bits), the Test Word (36 bits), and the Sense Switches (6 bits). The first two are used in conjunction with the operating push b.u.t.tons. The Sense Switches are present for manual intervention. The use of these switches is determined by the program (see System Block Diagram and Skip Group Instructions).

Operating Push b.u.t.tons

_Start_ - When this switch is operated, the computer will start. The first instruction comes from the memory location indicated in the Test Address Switches.

_Stop_ - The computer will come to a halt at the completion of the current memory cycle.

_Continue_ - The computer will resume operation starting at the state indicated by the lights.

_Examine_ - The contents of the memory register indicated in the Test Address will be displayed in the Acc.u.mulator and the Memory Buffer lights.

_Deposit_ - The word selected by the Test Word Switches will be put in the memory location indicated by the Test Address Switches.

_Read-In_ - When this switch is operated, the photoelectric paper tape reader will start operating in the Read-In mode. (see Input-Output).

In addition to the operating push b.u.t.tons, there are several separate toggle switches.

_Single Cycle Switch_ - When the Single Cycle Switch is on, the computer will halt at the completion of each memory cycle. This switch is particularly useful in debugging programs. Repeated operation of the Continue Switch b.u.t.ton will step the program one cycle at a time. The programmer is thus able to examine the machine states at each step.